AMD Bulldozer Notes

In a highly competitive industry where it's easy to divide the world into warring factions, each seeking to dominate their respective markets, it's always a relief to attend the International Solid State Circuits Conference (ISSCC). As a PR-guy (boo, hiss), I only have a cursory understanding of the papers being presented, and even those need to be explained to me by a patient member of AMD's technical team. But it doesn't require an EE degree to appreciate the energy of very bright people coming together to share ideas. Over the course of my career I've often seen engineers from sworn enemies in the market warmly greeting and laughing with each other at ISSCC. For a moment, much like the famed Christmas truce of World War I, the guns fall silent and the soldiers celebrate a common appreciation for pure technical achievement.

Over the years, AMD has regularly disclosed new details about its technologies at this event. Last year AMD disclosed the first technical information about the x86 core in "Llano," which served as a glimpse into the AMD Fusion APU strategy. In previous years, we've presented papers on AMD's DirectConnect Architecture as well as our GPU technologies. This is typically where industry watchers get a detailed peek into what is brewing within AMD's engineering teams.

ISSCC 2011, happening from 2/20 - 2/24, will be no different. AMD is releasing information about a few of its current and upcoming products, and we'll be using AMD's Bulldozer blog throughout the course of next week to update you on some of the details being disclosed for the first time about AMD's newest core design, "Bulldozer." If you want access to the complete conference proceedings, please register for the conference to receive them. Here are the basic areas being discussed:

Design Solutions for the "Bulldozer" 32nm: Showcasing AMD's 32nm technology and leading-edge design techniques, this session will discuss the power savings, performance improvements and new competitive features offered up by "Bulldozer". Session date and time: Monday, 2/21, 3:15 p.m.
40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD "Bulldozer": This session will be used to dive even further into the Bulldozer architecture to understand its out-of-order execution set and how the integer unit performs. Session date and time: Monday, 2/21, 3:45 p.m.
An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing: Interested in the technical and design details of "Orochi," AMD's upcoming high-end desktop and server processor? This session will discuss the new technologies and power-saving features used in the design. Session date and time: Tuesday, 2/22, 2:30 p.m.
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computer Devices: This session will look at AMD's first generation Fusion processor, the AMD E-Series APU, formerly codenamed "Zacate," which combines the power of an x86 CPU and AMD RadeonTM graphics manufactured on a 40nm die. You'll learn how it was designed and how to optimize performance and energy usage. Session date and time: Tuesday, 2/22, 4:15 p.m.

This year is already shaping up to be one of the most important years in AMD's history with the company continuing to churn out industry-changing products. We're excited about the upcoming "Bulldozer" x86 innovations and as soon as the doors close on ISSCC 2011, we'll be back in the trenches fighting to win our customers' business!

Gary Silcott is a senior PR manager at AMD. His postings are his own opinions and may not represent AMD's positions, strategies or opinions. Links to third party sites, and references to third party trademarks, are provided for convenience and illustrative purposes only. Unless explicitly stated, AMD is not responsible for the contents of such links, and no third party endorsement of AMD or any of its products is implied.

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AMD Bulldozer Notes

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